Imperas Software Ltd has released ImperasDV as an integrated solution for RISC-V processor validation. With this solution, SoC developers have a reliable, reference model-based validation solution that is compatible with the existing UVM SystemVerilog approach for SoC validation. At the same time, RISC-V's innovation and impact in design is driving new developments in all areas and applications of the semiconductor market.
Due to the wide range of configuration possibilities within the RISC-V specification, validation tasks previously required extensive setup and time-consuming manual adjustments to the established SoC design and validation process. This is especially true when custom extensions or modifications are added to the design process, as software-driven design styles check for additional custom feature optimizations and therefore often iterate with common hardware/software codesign.
The growing popularity of open source IP has also increased the number of teams using validation as an incoming quality check as part of the initial phase of SoC projects. In addition, the design options for modifying or extending the basic core functionality depend from the outset on the DV framework at work.
Key components include the Imperas RISC-V Gold Reference model, integrated test platform components, test suites, and professional support and training. ImperasDV is designed as a solution for easy, high-quality adoption of processor validation in established SoC DV processes based on UVM and SystemVerilog.
