Lattice Semiconductor announces the ECP5 Versa Development Kit to accelerate prototyping and testing of connectivity designs for small cell, microserver, broadband access and industrial video applications worldwide. The low power consumption, small form factor, and low cost of this series make it an ideal connectivity solution, and enable design engineers to quickly add features and functions that complement the functions and features provided by ASIC and ASSP, reducing This reduces development risks and speeds time to market.
To help users interested in the ECP5 device family quickly design and test application prototypes, Lattice has released the ECP5 Versa Development Kit. This kit enables customers to evaluate the connectivity performance of ECP5 FPGAs through a range of standards including PCI Express, Gigabit Ethernet, DDR3, and generic SERDES. Lattice also offers multiple proof-of-concept demonstrations through the ECP5 Versa Development Kit to help customers accelerate prototyping and design testing.
In addition, the ECP5 Versa development kit includes Lattice Diamond design software, which provides a complete set of FPGA design tools with an easy-to-use interface, efficient design flow, outstanding design exploration, and more. The company said that the Lattice Diamond software suite, tailored specifically for the ECP5 Versa suite, will be available for free to all users who purchase the board.
"When developing the ECP5 series, we broke all the rules of the conventional FPGA approach to provide a tailor-made optimal connectivity solution to meet the needs of compact, low-power, high-capacity communications and industrial applications," Deepak Director Boppana said product marketing at Lattice Semiconductor. "It turns out that ECP5 devices are the ideal companion chips for ASICs and ASSPs, and we believe that the new ECP5 Versa development board will only help further increase widespread adoption in the markets we serve."
Lattice has optimized the architecture of the ECP5 family with the goal of providing the best value under 100,000 LUTs, while adding key new features such as support for soft error correction and small packages of all densities. Compared with competitors' solutions, the cost of this solution is reduced by 40%. The optimization includes small logic chips based on LUT4, with enhanced routing architecture, dual channel SERDES to save chip space, and enhanced DSP modules, Increase resources up to 4 times.
