Cypress – New 4Mb family of asynchronous SRAMs with on-chip error-correcting code | Heisener Electronics
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Cypress – New 4Mb family of asynchronous SRAMs with on-chip error-correcting code

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Fecha de Publicación: 2015-05-27, Cypress Semiconductor Corp
Cypress Semiconductor announces sampling of new 4Mb asynchronous SRAMs with error correction code (ECC), a feature that enables them to provide the highest level of data reliability without the need for additional error correction chips – Simplifies design and reduces board space. These devices ensure data reliability in a variety of industrial, defense, communications, data processing, medical, consumer and automotive applications. Soft errors caused by background radiation can corrupt memory contents and cause critical data to be lost. The hardware ECC block in Cypress's new asynchronous SRAM family can perform all error correction functions online without user intervention, providing best-in-class soft error rate (SER) performance below 0.1 FIT / Mb (one FIT equivalent One error per error) Billion hours of device runtime). The new devices are pin-compatible with current asynchronous fast and low-power SRAMs, enabling customers to improve system reliability while maintaining board layout. The company said that the 4Mb SRAM also includes an optional error indication signal to indicate the correction of a unit error. Sunil Thamaran, senior director of Cypress's Asynchronous SRAM Business Unit, said: "We received a warm response from our customers for the 16Mb Asynchronous SRAM with ECC, which was the first device we introduced last year with an on-chip ECC family of SRAMs." "Adding new density to this family of products can benefit from our on-chip ECC technology, which expands the range of applications. Cypress is committed to developing new SRAM technologies to better serve our customers and further Consolidates our leading position in this market. " Cypress 4Mb asynchronous SRAM offers three options: fast, MoBL and fast with PowerSnooze-another energy-saving deep sleep mode that can achieve 15uA (maximum) for 4Mb SRAM Deep sleep current. Each option is available in industry standard x8 and x16 configurations. The device can operate at a variety of voltages (1.8V, 3V, and 5V) over the -40C to + 85C (industrial) and -40C to + 125C (Automotive-E) temperature ranges. The new SRAM is currently sampling in industrial temperature grades and is expected to begin production in July 2015. These devices will provide RoHS-compliant 32-pin SOIC, 32-pin TSOP II, 36-pin SOJ, 44-pin SOJ, 44 The company said that the product is available in TSOP II and 48-pin VFBGA packages.