Analog Devices - Dual ADCs feature an on-chip buffer and a sample-and-hold circuit (AD9684) | Heisener Electronics
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Analog Devices - Dual ADCs feature an on-chip buffer and a sample-and-hold circuit (AD9684)

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Fecha de Publicación: 2015-09-24, Analog Devices Inc.
14-bit 500MSPS LVDS AD9684 dual analog-to-digital converter (ADC) from Analog Devices. These devices have on-chip buffers and sample-and-hold circuits designed to achieve low power consumption, small size, and ease of use. The AD9684 ADC is packaged in a small 12mm x 12mm 196 spherical ball grid array (BGA) package, which provides high sampling rates for wideband analog signals, high linearity, and low power consumption. The AD9684 is optimized for wide input bandwidth and supports intermediate frequency (IF) sampling of signals up to 2GHz. Programmable threshold detectors use the ADC's fast detect output bits to monitor the input signal power. Because the threshold indicator has low latency, designers can quickly reduce the system gain to avoid over-range conditions at the ADC input. Dual ADC output data is routed directly to an external 14-bit LVDS output port that supports dual data rate (DDR) format. The SYNC ± input pin supports synchronization of multiple devices. In addition, the AD9684 provides flexible power-down options, which can save significant power consumption. Designers can program all functions of the AD9684 using a 3-wire serial port interface (SPI) with 1.8V to 3.4V capability. The AD9684 ADC is rated for the industrial temperature range of −40C to + 85C and is ideally suited for communications, diversity multi-band, multi-mode digital receivers, 3G / 4G, TD-SCDMA, W-CDMA, MC-GSM, LTE, universal -Dedicated software radio, UWB satellite receiver, instruments (spectrum analyzer, network analyzer, integrated RF test solution), radar, digital oscilloscope, high-speed data acquisition system, DOCSIS CMTS upstream receiver path and HFC digital reverse Path receiver, company.