DM74ALS165 is an 8-bit serial register that transfers data to the serial output QH when the clock is on. Parallel access to each phase is provided by eight separate direct data inputs enabled by a low level of SH/LD input.
Connection diagram
DM74ALS165 also features a clock suppression function and complementary serial output QH. When SH/LD remains high and CLK INH remains low, the clock is implemented by low-to-high conversion of the CLK input. The functions of the CLK and CLK INH(clock suppression) inputs are interchangeable. Since the low CLK input and the low to high CLK INH conversion will also complete the clock, the CLK INH should only change to the high level, while the CLK input is high.
Parallel loading is suppressed when SH/LD remains high. When SH/LD is LOW, the parallel input of the register is enabled regardless of the level of the CLK, CLK INH, or SER input.
Logic Diagram
